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Physical Design Chip Lead jobs

There are 978 Physical Design - Chip Lead-related jobs on Neuvoo India. Submit your application now and land the ideal job.

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Examples of corresponding job vacancies are Field Cashier, Pond Tender, Media Buyer, Supervisor Files, News Assistant or Geneticist. These job vacancies are often related to sectors like IT, Management, Computer, Engineering, Administration or Travel.

Employment statistics

Regions with the largest quantity of job vacancies related to 'Physical Design - Chip Lead' are Karnataka, Gujarat, Tamil Nadu, Maharashtra, Telangana or Odisha. Cities with the highest number of hits are Bangalore, Ahmedabad, Bangalore, Chennai, New Delhi or Pune.

Neuvoo India: the the largest job search website across India

Neuvoo India is the biggest job site in the country with over 1540825 vacancies available, 978 of which are Physical Design - Chip Lead-related.

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Talent Tattva HR Consultants Pvt Ltd |
Bangalore, Karnataka
- 1d ago
Of. the art and highly complex SoCs from Netlist to GDS. Hands. on technical leadership experience with... Macros and Full Chip Physical Designs. High level of expertise in complete physical implementation tool...
Allegro Solutions |
Ahmedabad, Gujarat
- 1d ago
Key Qualifications. The ideal candidate will have 8 years of physical design experience, with recent... PTSI, DC, OR EDS SoCEncounter(2) Taking care of full chip SOC PD issues (including Timing budget...
2COMS Consulting Pvt. Ltd. |
Bangalore, Karnataka
- 2d ago
10 years Experience in Physical Design implementationResponsible to own estimation, planning, execution and delivery of a medium to complex flat hierarchical full chip RTL2GDS...
Impact HR Services Pvt.Ltd |
Bangalore, Karnataka
- 2d ago
DescriptionTo perform Physical Design and Implementation related project activities for the MCU32 Division in a leading US based semiconductor company for Bangalore location. The product focus...
Impact HR Services Pvt.Ltd |
Bangalore, Karnataka
- 2d ago
DescriptionTo perform Physical Design and Implementation related project activities for the MCU32 Division in a leading US based semiconductor company for Bangalore location. The product focus...
Juniper Networks, Inc. |
Bangalore, Karnataka
- 13d ago
We have developed 3 generations of high end router chipsets. We have a track record of delivering 100... About The Position. We are looking to hire a Lead ASIC Design Engineer with excellent communication and...
JRS Communication |
Bangalore, Karnataka
- 5h ago
Experience working on Physical Verification for ASICs at Block level and Full chip level in Physical... Should be able to resolve Design Rule Checking (DRC), Layout vs. Schematic (LVS), antenna effects...
Allegro Solutions |
Ahmedabad, Gujarat
- 4d ago
Win solutions for the project. Lead physical design team with following responsibilities... planning, timing budget generation, power planning, IR EM Drop Flows, Full Chip Signoff STA, Block Level...
E Infochips Limited. |
Bangalore, Karnataka
- 4d ago
Working on Physical Verification for ASICs at Block level and Full chip level in Physical design flow... Key Skills. Should be able to resolve Design Rule Checking (DRC), Layout vs. Schematic (LVS), antenna...
Inveca |
(Unspecified city)
- 4d ago
Job Description. Job descriptionDigital Physical Design (PD) at Full Chip Level, SoC or IP Level in... Search Another Job. Similar Jobs to Full Chip Physical Design Lead Jobs. Physical Design Lead. Full Chip...
JRS Communication |
Bangalore, Karnataka
- 5h ago
Physical Design. Lead Engineers. Location. Bangalore, India. Minimum Educational Qualifications. B... Co ordinate the full chip physical design and verification activities. Physical design verification...
eInfochips Ltd |
Bangalore, Karnataka
- 3d ago
Job Description. Working on Physical Verification for ASICs at Block level and Full chip level in... Should be able to resolve Design Rule Checking (DRC), Layout vs. Schematic (LVS), antenna effects...
Qualcomm Technologies, Inc. |
Chennai, Tamil Nadu
- 3d ago
Well versed with parasitic extraction, LVS DRC and other Physical verification checks. Should be able to... years of experience in IC design Experience in leading block level or chip level Timing closure...
Allegro Solutions |
Ahmedabad, Gujarat
- 4d ago
Win solutions for the project. Lead physical design team with following responsibilities... planning, timing budget generation, power planning, IR EM Drop Flows, Full Chip Signoff STA, Block Level...
Talent HR Solutions |
Bangalore, Karnataka
- 2d ago
Block level SoC Physical Design including the Physical Design Verification(LVS DRC). Chip Level Floor Planning and EM IR efforts with Low power implementation methods. Pad Ring, ESD,EMC, Package...
Talent HR Solutions |
Pune, Maharashtra
- 1d ago
IO Timing closure2. Have lead atleast 3 tapeouts in complete flow of Physical Design. 3. Should have... . Should be able to handle some full chip level activities...

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Delhi (30)‎
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Karnataka (452)‎
Maharashtra (45)‎
Tamil Nadu (24)‎
Telangana (64)‎