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    78 jobs - Page 1 of 6 (0.08 seconds)
    Flex-I Partners
    |
    Bangalore, Karnataka
    - 5d ago
    Worked onNetlist to GDSII at block level for multiple tapeouts. Expertisein hierarchical partitioning of... Formalverification at various levels of design hierarchy with respect togolden RTL. Low PowerDesign...
    Wolverine World Wide, Inc.
    |
    Hyderabad, Telangana
    - 11d ago
    Experience in developing architecture micro architecture specifications, RTL coding, synthesis with DC... Knowledge of full RTL to GDSII flow to take timing closure from RTL to signoff. Good scripting skills...
    Qualcomm Technologies, Inc.
    |
    Noida, Uttar Pradesh
    - 11d ago
    Overview. The responsibility includes. Independent planning and execution of Netlist to GDSII... Work independently in the areas of RTL to GDSII implementation Ability to collaborate and resolve issues...
    Intel Corporation
    |
    Bangalore, Karnataka
    - 10d ago
    Qualifications. Minimum Qualifications BE B.Tech ME M.Tech MS in Electrical & Electronics Engineering with minimum of 10 years in VLSI Design with expertise in RTL to GDSII flow, floor planning...
    Intel Corporation
    |
    Bangalore, Karnataka
    - 10d ago
    Qualifications. Minimum Qualifications BSEE MSEE with minimum of 6. years in VLSI Design with expertise in RTL to GDSII flow, floor planning, Clock tree synthesis and block level chip level...
    Wolverine World Wide, Inc.
    |
    Hyderabad, Telangana
    - 11d ago
    Wired. Wireless. Design Implementation. Fully understands the implications of software on hardware design decisions Effectively exercises full design (Custom Semicustom RTL to GDSII...
    Wolverine World Wide, Inc.
    |
    Hyderabad, Telangana
    - 11d ago
    Taking design from RTL to GDSII. Owning and driving few aspects of design like synthesis, DFT , timing... Leading a timing signoff team to take a design from RTL to GDSII. Hands on ownership of one or more...
    Intel Corporation
    |
    Bangalore, Karnataka
    - 11d ago
    And Tcl. Familiarity with hardware description language such as Verilog. or System Verilog. Hands on experience in converging complex blocks from RTL to GDSII 100K 1 million gates with embedded...
    The Navigators
    |
    Bangalore, Karnataka
    - 3d ago
    Experience in leading block level or chip level Timing closure &. Physical Design activities. Work independently in the areas of RTL to. GDSII implementation. Ability to collaborate and resolve...
    The Navigators
    |
    Bangalore, Karnataka
    - 2d ago
    Experience in leading block level or chip level Timing closure &. Physical Design activities. Work independently in the areas of RTL to. GDSII implementation. Ability to collaborate and resolve...
    Mobiveil Technologies India Private Limited
    |
    Hyderabad, Telangana
    - 3d ago
    Requirements. Minimum 8 experience in RTL 2 GDSII Design. Experience in Sub micron Physical design methodologies and Physical Verification Should have exposure in Synthesis. DFT. Logical...
    Niranta Solutions
    |
    Bangalore, Karnataka
    - 7d ago
    The candidate should be proficient in all tasks related to RTL2GDSII including synthesis, floor planning, place and route, clock tree synthesis, Extraction, IR Drop Analysis, STA and timing...
    AMD
    |
    Hyderabad, Telangana
    - 11d ago
    Experience in developing architecture micro architecture specifications, RTL coding, synthesis with DC... Knowledge of full RTL to GDSII flow to take timing closure from RTL to signoff. Good scripting skills...