You will be part of design team to deliver next-generation Xeon Server CPU products.
Your responsibilities include : -
Contribute all aspects of the SoC design flow from high level design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing
Work closely with silicon architect and micro-architect in design definition, development of Architecture and Micro architecture specifications for the Logic components.
Perform logic design, Register Transfer Level (RTL) coding , integration and simulations for SOC
Contribute to the development of multidimensional designs involving the layout of complex integrate
Work with Validation team in defining validation strategy and reviewing test plan for design qualification & sign-off.
Bachelor of Engineering degree or Master of Engineering in Electrical and / or Electronics Engineering or related Engineering with 5+ years of RTL Logic design experience.
Experience in System Verilog, OVM / UVM, RTL development for high performance and low power design.
Well verse in interface timing budget, clock domain crossing design
Strong understanding of engineering design principles, methodology, tools / flows
Prior experience with CPU based SOC design is preferable
Working knowledge of memory buses, PCIe & other high speed interfaces will be a plus
Strong analytical and debugging skill and creative in problem solving
Good leadership, interpersonal and communication skills.
Inside this Business Group
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