Seeking a highly motivated individual, with expertise in IC design and physical implementation for a group with growth opportunities.
Responsibilities include floorplanning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, signal integrity, physical verification and DFM.
The individual will contribute both on the implementation side as well as flow development for advanced technology nodes
The successful candidate :
3+ years of physical design experience. Must have hands-on experience with design of complex ASSP and COT designs. Must also demonstrate knowledge of the Synopsys tools, flows and methodologies required to execute physical design projects.
These tools may include : Design Compiler, Physical Compiler, Primetime SI, ICC / ICC2, Star-RCXT, Hercules / ICV, HSPICE and other tools.