Assoc MTS,DFT Engineering
45d ago

Duties :

  • As a DFT engineer at Rambus, you will be responsible for Design, Implementation and verification of LBIST, MBIST, PBIST, SCAN, ATPG, Boundary Scan, P1500, IO BIST, JTAG etc.
  • on complex chips at advanced process technology nodes viz. 65nm / 40 / 28nm / 14nm etc.

  • Experience in SCAN insertion, Coverage analysis, debugging skills on faults, and enhancement is required.
  • You will be working on high speed and very low power designs.
  • Also involved in design and development of At-speed testing, complex DFT mode definitions, STA and Silicon bring up process.
  • Skills & Qualification :

  • UG- in DFT & RTL2GDS flow domain / DFT covering the following aspects.
  • Strong hands on Experience using Standard EDA Tools . Experience with logic simulators from one or more EDA vendor. Experience on Mentor Fastscan, Cadence’s encounter test, Tessent tools desired.
  • Reasonably good exposure in RTL2GDS flow tasks such as Synthesis, implementation, STA and IR drop
  • Strong understanding & hands on experience with industry standard DFT techniques such as boundary scan, Memory BIST, BISA and BIRA, Scan / on-
  • chip-Compression / ATPG / At-speed Fault simulation and Logic BIST and BIST for high speed serial links.

  • Post Silicon Validation, ATE Debug and Support are needed.
  • Very good understanding of the complete Logic design, Modeling, RTL-Implementation & Verification, Logic Synthesis, Logic Equivalent Checking & Static Timing Analysis.
  • Experience in fault grading, timing verification analog behavioral model validation and test vector delivery conversion flow desired.
  • Experience working with multiple complex chips at different technologies like 65nm / 40 / 28nm etc
  • Participate in driving new DFT methodology and solutions to improve quality, reliability and in-system test and debug capability
  • Programming in Perl and Tcl is a plus.
  • Apply
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