We are seeking an enthusiastic compiler engineer to work in a high-energy product development team delivering world-class EDA products to the industry.
Compiling high-level languages like Simulink and MATLAB into HDL code poses numerous challenges. Join us in solving these exciting problems and mapping state-of-art applications in computer vision, deep learning, and communications on to FPGAs and SoCs.
The engineer will be expected to design, architect, implement and test HDL friendly Simulink blocks targeting FPGA and ASIC devices.
Specifically, the engineer will be involved in all phases of product development :
Engage with customers and field engineers to gather requirements and expectations.
Design, architect and implement the HDL friendly algorithms, and HDL optimization features to enable a automatic HDL code generation for new functionality
Participate in testing the compiler in the different target environments.
Participate and collaborate with other engineers and teams to integrate the capability within the MathWorks software environment.
A bachelor's degree and 5 years of professional work experience (or a master's degree, or equivalent experience) is required.
Expertise with C++
Knowledge of compiler development
Exposure to algorithm development
Knowledge of HDL's such as VHDL or Verilog
Knowledge of FPGA / ASIC Development Cycle
Knowledge of Synthesis Tools such as Xilinx Vivado or Intel Quartus
Knowledge of tcl Script
Knowledge of MATLAB / Simulink / HDL Coder is a plus