Req Title Sr.Physical Design Engineer Location Hyderabad The candidate will be responsible for implementing the place and route of design blocks including floorplanning, placement, clock tree building, routing, timing optimizations, DRC, LVS fixing, IR drop analysis, Formal verification, power intent checks etc .
ampnbsp The candidate will also be responsible for block level physical design closure in terms of timing, power, DRCLVS etc.
REQUIREMENTS At least 12+ years experience in complex ASIC Design projects. Have in depth knowledge of entire physical design process from floorplan till GDS generation Good Exposure to Physical Verification Process Have handson experience in latest submicron technologies below 20nm Hands on experience in leading PnR tools Synopsys ICCCadence Encounter etc Experience in low power designs and handling congestion or timing critical tiles will be preferred Should be a quick learner and have good attention to detail Experience in ECO implementation preferred Scripting skills in PerlPython etc Must have good communication &amp problemsolving skills.
Should be able to handle PnR tasks with minimal supervision BachelorMaster Degree in Electronics EngineeringDesired Skills 1.
SoC implementation expertise. Multimillion gates integration.2. Physical Synthesis, Constraints validation.3. Floorplanning, Power planning.
4. Clock Tree Synthesis (CTS).5. Scan Synthesis, Scan reorder.6. Static Timing analysis (STA).7. Analysis IR, EM, Noise.8. Physical Verification.