Senior Verification Engineer - OTN/Python/System Verilog (6-8 yrs) Ahmedabad/Bangalore (Semiconductor/VLSI/EDA)
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Below Are the Job Details :

Experience : 6 to 8 yrs


  • Minimum 6 years- experience in ASIC / FPGA verification, including verification of complex ASICs at chip-level
  • Expertise in SystemVerilog / UVM
  • Knowledge of C and / or Python preferred
  • Networking protocol (i.e. Ethernet, OTN) and / or FEC experience is a must
  • Basic knowledge of SerDes and ADC / DAC a plus
  • Expertise in independently building SV / UVM test benches
  • Expertise in developing test cases and test plans
  • Functional coverage, code coverage closure experience a must
  • Gate sims and debugging.
  • Experience in lab validation and bring up activities is a plus
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