Network-on-Chip interconnect architecture aims to replace traditional interconnects, such as buses or crossbars, with one that is highly structured, with layered communication.
You will be working in deploying this technology across all kind of SoC, this technology which borrows some concepts from general networks, not only has the pin-to-pin replacement capability of more traditional methods, but also implements efficient, highly flexible and scalable solutions supported by a productive design flow. Minimum Qualifications
Ideal candidate should have minimum of 7 - 10 years of good experience in System C modelling and Performance Verification, with some experience RTL design, Micro-architecture
Preferred Qualifications NoC technology includes :
Configurable memory map and security scheme
Cache coherent infrastructure
Various protocol support (AMBA, custom interface for high performance multimedia IP, interNoC socket, configuration, )
Silicon debug units for efficient SoC bring-up
Quality of Service, buffering, splitting, shaping, and dynamic priority for complex SoC
High degree of configurability for PPA optimization
In addition, the technology is supported by advance modeling, design, verification, and silicon implementation tools.
The deployment Engineer must master the technology, and help SoC infrastructure teams to get the best PPA for the chip, and optimize the design and verification process of the Infrastructure.
Close interaction with SoC architecture is key to understand the requirements and help obtaining the best configuration.
In addition, the deployment engineer will gather feedback and drive the roadmap of the technology, both for the HW to be added or modified, and the various integration, verification and implementation flows