Seeking a highly motivated individual, with expertise in IC design and physical implementation for a group with growth opportunities.
Responsibilities include floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, signal integrity, physical verification and DFM.
The individual will contribute both on the implementation side as well as flow development for a variety of mixed signal IP & Subsystems products and test-chips at 16 nm and below.
The successful candidate :
has solid engineering understanding of the underlying concepts of IC design
has intimate knowledge of the full design cycle from RTL to GDSII, including development of timing constraints
is an expert with the implementation flows and methodologies for deep sub-micron designs
has experience in high performance digital design and CAD, high-speed design, low-power design, high speed clock design and distribution.
has proven experience contributing to project tape-outs.
has experience in timing closure, signal integrity.
has good software and scripting skills (Perl, Tcl, Python, .); knowledge of CAD automation methods.
Can contribute to enhancing the best practices of the physical design flow
Can interface with the larger product team to understand design constraints, deliverable formats, customer requirements
Independent, timely decision maker and able to cope with interrupts
Must possess knowledge of IC Compiler and IC Compiler II is preferred
Knowledge of IP Subsystem implementation is an added advantage.
BS or MS with 10+ years of related experience. Must have hands-on experience with design of complex ASSP and COT designs.
Must also demonstrate knowledge of the Synopsys tools, flows and methodologies required to execute physical design projects.
These tools may include : Design Compiler, Physical Compiler, Primetime SI, ICC2 / FC, Star-RCXT, Hercules / ICV , IREM analysis and other tools