This opportunity exists inside the Intel Programmable Solutions Group (PSG) engineering organization which develops FPGAs, ASICs, and Structured ASIC products.
The IP and Solutions engineering team is responsible for delivering Networking and SmartNIC IP and solutions as part of the Platform Solutions Group.
This is a high visibility role in the IP and Solutions Engineering organization of PSG to lead the SmartNIC IP development for PSG for their next generation flagship product.
The PSG IP and Solutions Engineering team is seeking an experienced Design Verification Manager to help define and lead the next generation FPGA IP solutions for Ethernet, SmartNIC, Networking and Communications segments for programmable logic products.
This forward-looking dynamic role provides unique opportunities to influence future product direction requiring a strong technical leader with strong leadership.
personal communication and collaboration skills. The successful candidate will bring design solutions experience for Data Center, and / or Communications, Networking, and / or Wireless domains, ideally covering both hardware and software, with knowledge of FPGA architecture, transceiver architecture and higher level protocols.
Ideally the candidate will have experience leading large design teams on strategic projects implementing designs for FPGA and / or ASIC Expertise in networking and storage would be a distinct advantage.
You will lead a complex global IP Solutions program driving various aspects of the functions including design, verification, timing closure, software drivers, hardware verification.
You will work with cross-functional teams including planning, architecture, silicon design, software and platforms to define and drive delivery of holistic customer solutions that meet market requirements and capabilities comprising silicon, soft IP, applications, SW and tools support.
Manage overall program including planning, tracking, execution, executive reporting. Align with global stakeholders in various sites, anticipate and mitigate risks.
Overall responsibility for quality and execution. Track the resourcing and schedule requirements of the program and manage required contract worker engagements.
15 years of experience with a MS degree in design and verification of complex networking, Ethernet based IPs and subsystems.
Good understanding of FPGA IP design and implementation methodology. Should have experience in all phases of IP and solutions design ranging from architecture, RTL design, Verification, timing closure and hardware validation.
Strong experience with verification flows and methodologies with hands-on experience with UVM, OVM. Should have managed complex IP solutions programs end-to-end.
Good communication and presentation skills a must. Should have ability to work in multi site execution and ability to influence across groupsStrong experience in networking standards and protocol.
SmartNIC design experience is a big plus.