Principal Engineer - Physical Design
Microchip Technology
Bangalore, IN
3d ago

Company Description

Microchip Technology Inc. is a leading provider of embedded control applications. Our product portfolio comprises general purpose and specialized 8-bit, 16-bit, and 32-bit microcontrollers, 32-bit microprocessors, field-programmable gate array (FPGA) products, a broad spectrum of high-performance linear, mixed-signal, power management, thermal management, radio frequency (RF), timing, safety, security, wired connectivity and wireless connectivity devices, as well as serial Electrically Erasable Programmable Read Only Memory (EEPROM), Serial Flash memories, Parallel Flash memories, and serial Static Random Access Memory (SRAM).

We also license Flash-IP solutions that are incorporated in a broad range of products.

Job Description

To support Physical Design-related project activities for the MPU32, MCU32, and WSG Business Units in Microchip. The product's focus is on 32-bit microprocessors, microcontrollers, and wireless design and implementation.

Job activities :

  • Implement all aspects of physical design such as floor planning, placement optimization, clock tree, synthesis, routing, crosstalk avoidance, and physical verification
  • Utilize hierarchical systems-level design techniques to build designs exceeding multi-million gates.
  • Working on the place and route methodologies and low power methodologies.
  • Must be a self-motivated team player who can collaborate with multiple teams across a geographically diverse company to achieve desired design goals.
  • Detailed job functions include :

  • Timing closure support to maximize process node capability.
  • Clock tree setup / debug and synthesis for optimal QoR.
  • General physical implementation procedures.
  • Multi-voltage island-based floorplan design and support.
  • Flow development and automation implementation.
  • Delivering Physical Verification-clean designs.
  • Die size estimation and Bond out approval.
  • Interfacing with external vendors and IP sources to resolve problems.
  • Working with members from international design / implementation teams.
  • Job Requirements

    The successful candidate will have a minimum of 5 years or more applicable technical experience in the chip assembly process, which includes physical and timing-related aspects of IC design.

    The design task requires experience in the following Physical Design-related activities :

  • Advanced knowledge of VLSI logic principles, clock tree synthesis & debug, and design timing closure.
  • Advanced knowledge of place and route methodologies and low power methodologies.
  • Experience with 40nm or 28nm technologies is required.
  • Recent experience with leading full-chip Physical Design activities.
  • Detailed systems-level floorplanning.
  • Power network planning.
  • Multi-voltage / low power implementation techniques.
  • Power integrity and reliability (EM & IR) analysis.
  • The successful candidate should have :

  • Detailed knowledge of ICC / ICC2 or Innovus and Redhawk toolsets.
  • Proficiency in Tcl and Perl scripting is essential.
  • Excellent debugging and analytical skills.
  • Good verbal and written communication skills and strong interpersonal skills.
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