Physical Design Verification Engineer - Floor Planning/Signal Integrity (2-5 yrs) Bangalore (Semiconductor/VLSI/EDA)
Infinity HR Consulting Pvt Ltd
Bangalore, India
1d ago
source : hirist.com

Job Description :

  • You will be working on the Implementation of multimillion gate SoC designs in cutting edge process technologies (28nm, 16nm, 14nm, 7nm - )
  • Work on all aspects of physical design including Floor Planning, Power Plan, Integrated Package and Floorplan design, Place and Route, Clock
  • Planning and Clock Tree Synthesis, complex analog IP integration, Parasitic Extraction, Timing Closure, Power / IR Drop,
  • Signal Integrity Analysis, Physical Verification (DRC, ERC, LVS), DFM and DFY and Tapeout. You will be required to innovate on the flows to meet the QoR targets and ensure predictability.
  • You will be exposed to the latest processes and will be required to develop the flows to meet best in class PPA.

    Skills :

  • Physical design verification tasks include creating setup and scripts for DRC, LVS, Antenna and density checks, report generation, analysis, debug and implementing the fixes in the physical design database.
  • This also includes DFM checks for the advanced node designs.
  • Ensure correct IP and pad-ring integration designs.
  • Also involve in chip planning, floor planning and power route planning.
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