Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies -
Wireless / 5G and Wired Communications; Automotive / ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others.
Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI).
Our global team is growing and we are looking for bold, collaborative and creative people to help us lead the industry transformation to build an adaptable intelligent world.
We believe that by embracing diverse ideas, striving for excellence in all that we do, and working together as a unified team, we can accomplish anything.
Come do your best work and live your best life as part of the ONEXILINX team
Xilinx is looking for a talented individual to join the design group in the position of Staff Design Engineer to provide technical leadership towards the development of high speed memory controller designs (operating above 6.
4 GHz data rate). This person will possess a deep knowledge in system level challenges, logic design and strong experience architecting complex high speed IP's.
The successful candidate will work as a contributing member and as a lead of a team responsible for the architecture and design of next generation memory interfaces for Xilinx customers.
Responsibilities include leading technically a team of designers, resolving system level challenges, architecting, implementing, documenting and validating the memory controller IP cores.
The area of focus would be on high speed memory interfaces like DDR5, LPDDR5 DDR4, LPDDR4, and RLDRAM3. The candidate must have excellent inter-
personal and communication skills and be able to work independently. Xilinx holds a strong position in the FPGA all programmable paradigm.
This position offers candidates exposure to the latest generation IP, tools, boards, FPGA products and the ability to design and develop high speed memory IP cores.