Lead STA Engineer
NXP Semiconductors
3d ago

Must have

  • Strong Constraints, Synthesis and STA experience
  • Strong Experience in interface timing closure(USB, PCI express, I3C, SPI.....)
  • Exposure to Low Power implementation flow
  • Expertise in clock tree closure from Frequency / Power / EMC / Reliability perspective.
  • Experience in all Physical Design tasks related to Mixed Signal Chips(Analog On Top or Digital On Top) will be a plus
  • Strong scripting skills to automate the flow.
  • Exposure to Cadence tools.
  • Should have good communication skills
  • Should be a good team player.
  • Experience

  • Self-Starter with at-least 8 years of relevant experience Exposure to STA & timing closure Analog and Digital Integration Rules as well as P&R is a plus.
  • Be fluent with physical design Concepts and Tools.
  • Drive technological innovations in the team
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