Intern-Design Engineering
3d ago

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

  • Good Logical reasoning , Some knowledge of Verilog data types , block / non blocking , arrays , verilog timescale events , system verilog New data types , packages , struct , testbench interface & components .
  • Basics of Design Verification flow, metrics (Functional Coverage, Code coverage, Assertion development / closure) and debug skills knowhow.
  • Mixed Signal verification experience from project work (if any)and / or knowledge of Cadence digital / analog verification tool is an added advantage.
  • Basic concepts of SerDes IP is preferred.
  • Hardworking, Committed and willingness to learn.
  • We’re doing work that matters. Help us solve what others can’t.

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