Working closely with the pre-silicon project teams, your responsibilities will include development and delivery of one or more of the following : -
re-usable validation content for standard bus protocols and other shared architectural features-bus functional models for common bus protocols and other high-
level architectural components-design configuration information, memory topologies, and system address maps-general testbench and simulation infrastructure support-
software management and continuous release methodology-creation and optimization of the validation environment, tools, and methodologies
BE with 5+ years of relevant experience or ME / MTech with 3+ years of relevant experience -Ability to develop SystemVerilog TestBench code, along with randomization and constraints.
Strong background in computer architecture-Scripting languages and shell scripting-Knowledge of C++ and SystemC-Software design patterns-
Experience in pre-silicon or post-silicon validation / verification-Outstanding communication and team work skills-Excellent hardware and software debug skills
Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms.
PEG strives to lead the industry moving forward through product innovation and world class engineering.
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