At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Cadence’s Virtuoso enables verification and implementation of complex IC and package designs at advanced and mature technology nodes.
The Virtuoso platform is being enhanced to support RF package designs, this will help designers analyze and implement the chip and package on a unified platform in RF domain.
We are seeking software engineers to help us solve challenges such as :
Enable Schematic design and editing in IC and package design
Verify and analyze impact of parasitic components on the behavior of the design using advanced analysis environment like ADE, APS and 3D-EM solvers et.
Co-Design methodologies working with schematic, IC design and package in a unified platform
Transformations in IC design and package, using computational geometry concepts
Comparison analysis challenges, on cross fabric designs, along with GUI development to help user analyze and debug variations.
Primarily C++. You'll learn SKILL, Cadence's proprietary Scheme-based language. Other technologies include QT, and GUI development concepts.
Requires Bachelors degree in Computer Sciences or Electrical and Electronics with CSE electives.
Requires experience with OO development and data structures analysis and design.
Masters Degree will be preferred but not a must requirement.
We’re doing work that matters. Help us solve what others can’t.