Senior ASIC Physical Design Engineer
In this role, candidate will be part of the engineering team implementing DDR and HBM PHYs for customer ASICs and SOCs in DDR and HBM PHY Hardening service line, which includes front-end implementation, physical design, timing and physical verification, design for test and ATPG.
Candidate will contribute as a senior member of a design team, or as a project design drive working with both internal and external design teams.
Ideal candidate for this role demonstrates excellent technical knowledge, excellent verbal and written communication skills, and awareness of project management issues.
Keeps composure during crises and can comfortably handle risks and uncertainty. This position has a sound desire to learn and explore new technologies.
Demonstrates good analysis and problem-solving skills. Prior knowledge and experience with state of the art CAD tools and technologies is required.
Exclusively works in all place and route flow stages : Synthesis, Floorplan, Power Plan, Placement, CTS, Routing, STA and Physical Verification.
Performs in project leadership role. Contributes to complex aspects of a project, resolves and develops approach to solutions.
Work is self-starter and collaborative in nature. Provides regular updates to manager on project status. Represents the organization on business unit and / or company-wide projects.
Coaches and mentors junior team members, and guides them in execution of their jobs. Frequently networks with senior internal and external personnel in own area of expertise.
Key Qualifications :
A relevant degree in Electrical Engineering or Computer Science
Significant experience (6 years or more) in ASIC physical implementation and place and route flows.
Knowledge of industry standard data file formats : Verilog, GDSII, LEF, DEF, SDF, SPEF, LIB
Scripting and programing skills : TCL, Unix Shell, Perl, Python
Verbal and written fluency in English.
Exceptional cross team communication skills, team leading experience and tuition of junior engineers
Practical experience with any P&R tool set
Practical experience with Synopsys PnR tool set : Design Compiler, IC Compiler(2), Fusion, Prime Time, IC Validator
At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence.
The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security.
If you share our passion for innovation, we want to meet you.
Our Silicon IP business is all about integrating more capabilities into an SoC faster. We offer the world’s broadest portfolio of silicon IP predesigned blocks of rationale, memory, interfaces, analog, security, and embedded processors.
All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications.
And get differentiated products to market quickly with reduced risk.
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.