SOC Design Implementation - Sr Lead Engineer
Qualcomm Technologies, Inc.
Chennai, India
6d ago

Job Overview

The position is responsible for full chip level synthesis and timing constraints, power aware physical synthesis and formal verification Formal verification for RTL 2 gates and gates2gates UPF 2.

0 based power aware equivalence checking using Conformal. Debugging PA-FV failures Conformal ECO for doing complex functional ECOs.

Low power synthesis on smaller blocks and subsystems using DC / Genus Physical Aware synthesis Minimum Qualifications Formal verification for RTL 2 gates and gates2gates

UPF 2.0 based power aware equivalence checking using Conformal.

Debugging PA-FV failures

Conformal ECO for doing complex functional ECOs.

Low power synthesis on smaller blocks and subsystems using DC / Genus

Physical Aware synthesis

Preferred Qualifications Formal verification for RTL 2 gates and gates2gates UPF 2.0 based power aware equivalence checking using Conformal.

Debugging PA-FV failures Conformal ECO for doing complex functional ECOs. Low power synthesis on smaller blocks and subsystems using DC / Genus Physical Aware synthesis Knowledge of DFT fundamentals

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