As a Layout Engineer, you will be responsible to perform I.C. mask layout design and physical verification on mixed signal designs.
You will be responsible for independently planning and executing the Layout, lvs / drc / antenna checks on complex analog mixed-
signal integrated circuits. You will work very closely with circuit designers and CAD engineers, to perform custom mixed-
signal blocks layout. Adherence and maintenance of already established companywide layout design & CAD methodologies and process flows.
BSEE / CSEE and
2-5 years of industry experience in mixed signal CMOS IC layout design at block & chip top level, including chip floor planning and integration
Must have proven track record as a lead layout engineer in coordinating and delivering the full chip layouts under tight schedule constraints.
Must have experience in handling full chip layout and integration using state of the art I.C layout tools
Experience with Cadence Virtuoso-XL and Mentor Graphics Caliber physical verification tools is a must.
Must have good understanding of the analog layout techniques such as device matching, shielding etc.
Must be experienced in the layout of ESD devices and I / O circuitry.
Must have good working knowledge of Linux operating system.
Skills in development of standard and custom analog cell libraries.
Experience in DRC, LVS, ERC, Antenna, and post layout extraction.
Experience with foundry command deck, PDK, fabrication & mask process
Tapeout flow experience, Jobdeck review of fractured mask data (MEBES)
Must have good verbal and written communication skills and experienced in creating documents using Microsoft office