Principal Engineers at Intel are active technical leaders inside and outside the company. Activities include driving key technologies besides participation in major industry and academic conferences, voting membership in international standards committees, generation of patents and technical papers.
Responsible for working with standards bodies in high speed serial IO-Technology controllers domain (like PCIe, CXL and / or adjacent standards) with goal of of Defining and Driving 'state of the art digital controller IP-stack roadmap and solutions (including MAC, Link Layer, transport layer) with best in class KPIs'.
Responsibilities would include owning the end to end IP stack development from architecture concept to production quality IP including (but not limited to) defining roadmap, RTL microarchitecture, pipelines, review IP verification strategies & plans , mentor senior RTL designers on execution & best in class quality, support post silicon / emulation teams for any debug etc.
You must possess a degree in electronics / electrical / communication / VLSI / Microelectronics and / or related engineering / technology with experience in the range of 18 to 28 years in defining specifications / architecture & execution of RTL / Logic design of IPs in high speed serial IO domain (PCIe / CXL etc) .
Publications and patents in relevant fields would be an added advantage.
Below are some of the specific expectations for this role