At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence.
The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security.
If you share our passion for innovation, we want to meet you.
Our Silicon IP business is all about integrating more capabilities into an SoC faster. We offer the world’s broadest portfolio of silicon IP predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors.
All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications.
And get differentiated products to market quickly with reduced risk.
ASIC Digital Design Engineer Staff
We're looking for an ASIC Digital Design Engineer Staff to join the team.
Does this sound like a good role for you?
You will be part of the Solutions Group at our Bangalore Design Center, India. This is a Technical Individual Contributor role and offers challenges to work in a multi-site environment on technically challenging IP Cores in the Design & Directed Verification domain.
Understand Standard Specifications / the functional specifications / feature enhancements for the product and create micro-architecture and detailed design documents for some of the components of the design with medium complexity.
Be an individual contributor in the Design Tasks RTL coding of design, debug, verification coverage improvement in the directed Verilog Test Bench, etc.
Create / work on designs using Low Power Design Methodology and automotive safety
May need to understand Standard Specifications / the functional specifications / feature enhancements for the product and create micro-architecture and detailed design documents for some of the components of small complexity functions / product features for the DesignWare family of synthesizable cores in protocol areas such as AMBA (AMBA2, AXI, CHI) / SD / eMMC / DDR / PCIe / Ethernet / USB / MIPI
Creates deliverables which do not require close review or supervision by a Senior Technical Lead.
May learn to do technical review of RTL Code of small / medium complexity.
The candidate should be able to analyze the coverage metrics and improve them with definition of additional test cases in directed environment, at least for small / medium complexity features of the protocol / product specs.
The candidate will work in a project and team-oriented environment with teams spread across multiple sites, worldwide.
Key Qualifications and Experience
Must have BSEE in EE with 14+ years of relevant experience or MSEE with 12+ years of relevant experience in the following areas :
Design of IP Cores or SoC Designs for Set Top Boxes, Mobile handsets, Smart Devices, etc.
Knowledge of one or more of protocols : AMBA (AMBA2, AXI, CHI) / SD / eMMC / DDR / PCIe / Ethernet / USB / MIPI
Hands on experience with creating micro-architecture / detailed design from Functional Specifications for small / medium design complexity.
Must have worked on control path-oriented designs like asynchronous FIFO, DMA architectures, SPRAM / DPRAM interface design, etc.
Ability to technically lead small teams of size 6 to 8
Hands on experience with Verilog / System Verilog coding and Simulation tools
Synthesis flow and static timing flows, Lint, CDC, Formal checking, etc is a must for candidates with design background
Knowledge of C
Experience with Perforce or similar revision control environment
Knowledge of Perl / Shell scripts.
In addition, the candidate should have good communication skills, should be a team player and possess good problem-solving skills.
Experience of working with Functional safety, ISO26262 , FMEDA are a clear advantage
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.