4+yrs of expereince in ASIC Design.
Expertise in understanding, gathering and finalizing the requirements for ASIC / SOC design.
Implementation for SOC / IP Design and full chip integration
Competent in basic digital design concepts, interfacing, clocking, setup-hold timing concepts, multi-clock design
Hands on experience in Verilog / VHDL / System Verilog for design.
Hands on experience in NCSIM / Modelsim / VCS / QuestaSim.
Good in debugging.
Hands on experience in CDC / Linting, Synthesis, Static Timing Analysis and LEC
Knowledge of some of the interface protocols like PCIe, USB, SATA, MIPI etc.,) preferred
Responsible for development, support, maintenance, Implementation and Testing of complex components of an BASIC / SOC / FPGA / Board.
Work on problems of complex scope, through general usage of standard programming concepts and principles and application of own judgement.
Responsible for the circuit design, circuit debugging, Design entry using HDL, Integration, Simulation,schematic entry,layout & verification of complex components .
Requires extensive knowledge of at least one design area. Is able to analyse, resolve complex issues in his work area with very less assistance.
Has the ability to respond to detailed queries. Applies own judgement to independently determine a course of action, which is then executed independently post review.
Responsible for coaching, guiding and mentoring junior members in the team to help them scale up faster.