Role & Responsibilities : 1) Modeling : - The candidate will be responsible for leading a small team in doing development and maintenance of the front-
end views like Verilog simulation models, DFT and ATPG models, UPF and CPF models, etc for Standard Cells and Interface physical IP.
The candidate would be responsible for driving methodology development for Physical IPgeneration and validation by understanding the IP view requirement from SoC implementation perspective.
quality solutions for the engineering community. - He will also be responsible for driving engagements with EDA partners to explore new EDA solutions impacting our Physical IP deliverables for Logic and Interface IPs.
Qualification & Experience : - Bachelors or Master's Degree in Electronics Engineering or equivalent - 7-10 years of engineering experience in area of Physical IP development Characteristics & Requirements : -
Quick learner, good problem solving and debugging skills - Willingness to be flexible and accept new challenges - Capable of leading a small team -
Ability to work cross sites and cross teams - Ability to engage with external customers and EDA partners - Good analytical and reasoning skills -
Enthusiastic and self-motivated Essential Technical Experience : - Good understanding of digital circuits fundamentals and SoC concepts -
Experience with Verilog modeling and verification - Experience with Frontend flows like Simulation, Synthesis, ATPG and Logic Equivalence -
Familiar with Analysis tools like Timing, Power, Noise, etc - Familiar with source control systems like Synchronicity or SVN -
Working knowledge of scripting tools (TCL, Perl) Desirable Technical Experience : - Experience with System Verilog based verification -
Working knowledge of CPF / UPF - Low power flows - Working knowledge of Spice simulation - Familiar with Backend tools like Place and Route, Extraction, etc. (ref : hirist.com)