Develop pre-Silicon functional validation tests to verify system will meet design requirements. Create test plans for RTL validation, defining and running system simulation models, and finding and implementing corrective measures for failing RTL tests.
Analyzes and uses results to modify testing. VLSI design and verification experienced with ASIC design flow, Verification of digital designs inclusive of module and top-
level chip level SoC designs, Test bench architecture and development, State of the art verification methodologies and flow, independent creation of test benches / test cases, verify module and top-
level designs, Gate level simulations and understanding of Emulation and FPGA prototyping. Responsibility will include but not be limited to : -
Validating designs at block or full-chip level by authoring validation plans, writing focus tests, creating templates defining coverage strategies, developing and analyzing coverage monitors, creating event injectors, writing architectural and micro-
architectural correctness checkers, developing BFMs Bus Functional Model, running functional simulations, and debugging failures.
oriented environment and interacting with engineers from other design disciplines. Intel CHD group develops Broadband Communication Technologies & Semiconductor solutions for modems for networks and digital homes.
Its holistic solutions of broadband technology, complete applications, communication standards enables the company to offer the broadest portfolio of highly integrated, flexible end-
to-end semiconductor solutions for next generation networks and the digital home. The Company's advance SoC system-on-chip solutions address a wide variety of technologies, including GPON, xDSL / G,fast modems, WLAN Access Points, DOCSIS cable modems and being a significant supplier of access network integrated circuits.
The group core expertise is to combine world-class mixed signal and digital signal processing to deliver Innovative system-
on-chip integration. The activities at CHD India span from algorithm modelling, Architecture definition, specification development of the IC's and system who owning world-
wide responsibility of the Chip development, Firmware architecture & firmware development, Software architecture & Software development and Customer Support.
Solutions enable global system manufacturers to gain a commercial edge and create high-speed data and communication products which drive innovation in this market and deliver value to carriers and operators.
Master's degree in Electronics / Electrical Engineering, with concentration on Communications, Signal Processing and VLSI Design .
10+ years of industry experience in verification of complex IP blocks, subsystems and SoC. Proficient in writing and debugging tests in UVM / system verilog as well as C.
Experience with assertion-based verification using industry standard formal verification tools. Experience in coding UVM test benches, reference model development, scoreboards and monitors for IP, Subsystems and SoC, Third Party VIPs usage.
Understand the various SoC integration verification aspects like connectivity, IP integration, use case verification, Performance tests, Stress tests and system tests.
knowhow on PCIe Gen 1 / 2 / 3 / 4 , Ethernet, High speed PHY's and Processor Subsystems will be value added. Familiarity with Scripting Languages like Gmake / Perl / Tcl / Python.
Strong verbal and written communication skills and the ability to work with a team spread across different geography sites.
Flexible in dynamic execution environment
Inside this Business Group
The Client Computing Group is responsible for all aspects of the client computing business across Phone, Phablet, Tablet and PC platforms, leading Intel's efforts to transform client computing through technologies, new form factors, and driving Intel's corporate-
wide user experience initiatives. This spans all client device brands including hardware, software and connectivity ingredients for phones, tablets, Ultrabook™, All-
in-Ones, 2 in 1 computing devices, and home gateways.
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