Enphase is looking for experienced SoC RTL design engineers to join our newly formed team in Bangalore India. The team is being formed to bring our next generation Control ASIC to production in a 28nM or 22nM technology.
This new ASIC will use the ARM CM4 core, so experience with that core is a must. This new SOC will be integrating safety and security features into this next generation of MCU so a deep understanding of these SoC challenges is required.
Similar to many other SOCs, our Control ASIC includes the CPU as mentioned above, a large Analog Front End (AFE) consisting of references, clocks, multiple ADCs, DAC functions, and analog muxes for the needed measurements in the Inverter, a Power Line Communications Modem (PLC), our proprietary Power Production control block and a host of other peripherals.
This position is in our ASIC Engineering Team Reporting to the Senior Director of ASIC Engineering in Bangalore India.
Working with our Architects and IP designers you will develop the integration methods and integrate the full chip for handoff to our ASIC vendors for the layout and timing closure.
Deep understanding and experience in SoC architecture and integration
Specific experience integrating the ARM CM4 and all the surrounding IP, like : AHB, AXI, RAM and ROM controllers, DMA controllers.
As our new MCUs will include security features for the first time, experience with the ARM Protection units is preferred.
At minimum, experience with one of the TrustZone like IP from other vendors. As these Control ASICs from Enphase contain a large AFE, experience with integrating high speed and high accuracy analog systems is a must.
Hands on micro-architecture and RTL coding is mandatory.
Knowledge of all the Soft IP collateral and deliverables eg : Lint, CDC, UPF, Synthesis, MVRC, LEC and timing constraints is highly preferred.
Experience and ability to shape and direct our future IP and SoC integration methodology.
This position is based in Bangalore
Proven track record based on at least 15+ years of experience.