Conducts or participates in multidisciplinary research in the design, development, testing and utilization of Frontend RTL Designs.
Prepares specifications, develops top-level architecture, partitions design, codes and analyzes test reports. Develops plans and cost estimates and assesses projects to analyze risk.
Initiates, guides, and coordinates overall design and development of new ideas and products. Design, RTL coding and Test Bench verification of the custom RTL for CPU / FPGA based hardware boards.
Design efforts includes understanding architecture requirements to come up with design specifications, RTL design document, RTL coding, TB coding, support and release of relevant documents and test plans.
Ensures that custom RTL conforms to standards and specifications specified in the architecture requirements. Lab work predominantly at Intel India Bangalore involves supporting board bring-up team, functional, electrical and stress validation along with FPGA debug.
Tool knowledge required for board debug and validation - Oscilloscopes, FPGA programming and debug tools, logic analyzer etc.
Strong verbal communication and presentation skills. Ability to work independently and some knowledge in Excel Macro and scripting languages such as Perl / Python is an added advantage.
Responds to customer / client requests or events as they occur. Develops solutions to problems utilizing formal education and judgement.
Candidate will be responsible for
Logic Design, RTL coding
Running through RTL design verification flow and simulation
Defines Module level Interfaces
Board level testing and debug
Handling cross-functional team meetings.
Good at decision making
Leading a team of 5 RTL design engineers
12+ years of experience with Bachelor's or Master's Degree in Electronics and / or Electrical Engineering
Proficiency with RTL coding using HDL language(s)
Experience with Embedded Software Development Kit based SoC designs.
Experience in test bench based RTL simulation, debug and code coverage analysis.
Experience in Clock domain crossing / Timing analysis.
Experience in defining FPGA constraints
Script level verification / validation knowledge
Experience with bit file generation, image programming, Board level testing and debug.
Strong communication skills, able to handle cross functional team meetings.,