Senior Staff DFT Engineer
Bangalore, KA, IND
2d ago


include DFT architecture, RTL coding, simulation and verification, chip testing and supporting Automatic test Equipment (ATE) issues.

  • Develop DFT methodologies that reduce test cost, increase product quality, and enhance yield learning on leading edge process technologies.
  • Job responsibilities include DFT pattern generation, coverage analysis and debug as well as running and debugging gate level simulations.
  • Work with the Test Engineer to bring up ATPG and MBIST pattern on the ATE. Resolve any issues which show up during characterization.
  • Qualifications

  • Should have solid understanding of Fault modelling, Scan compression, Memory testing techniques.
  • Hands on experience on all aspects of DFT flow, including DC / AC scan, ATPG, JTAG / boundary SCAN, memory BIST, high speed interface test.
  • Demonstrated understanding of the entire ASIC design flow; logic design, Verilog / VHDL verification, synthesis, timing and backend.
  • Track record of supporting a large volume of commercial SOC shipments
  • Excellent analytical and debugging skills and the ability to proactively solve issues.
  • Must be able to work autonomously and guide others based on changing priorities.
  • Proven ability to thrive on, learn and adapt to new methodologies and technologies.
  • Excellent oral and written communications skills.
  • Bachelors + 8 years’ experience / Masters + 7 years’ experience / PHD + 3 years’ experience
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