In this position, candidate will be responsible to lead the FEBE team and be interface with Front-end team to resolve the RTL related issues associated with clock domain crossing, responsible for full clocking architecture , defining clocks as per design specs.
Candidate is responsible for partition synthesis, SoC synthesis for validation design collateral e.g UPF, constraints and scan configuration setting.
Identification of critical paths based upon full chip timing model & working with RTL team to resolve the same.
This includes, drive the team to resolve issues in clock domain crossing, validating clock constraints, validating exceptions / constraints using Fishtail.
Closure of timing at chip-level with zero wire load for both functional & scan mode. Working with IP team to resolve IP issues associated with CDC waivers, CDC model issues etc.
Hands-on experience in resolving low power checks, UPF modification & formality / LEC debug capability.
Candidate will also be involved to interact with Full Chip Timing (FCT) team on timing issues and working with RTL team to resolve hard rock path.
You will also be responsible to drive the methodology development in critical design issues, troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention.
In addition, be self-motivated with the initiative to seek constant improvements in design, flow & methodology.
The candidate must also possess strong initiative, analytical / problem solving skills, team working skills, ability to multitask and be able to work within a diverse team environment.
You must possess a Bachelor of Engineering degree or Maser of Engineering in Electrical and / or Electronics Engineering with 10 relevant experience with the skills in Clock domain crossing, Fishtail / GCA, timing analysis, Low power checks, synthesis, APR flows.
Additional qualifications include :
Good understanding of Place & route challenges in multi voltage design.
Experience with UNIX, Perl and TCL also desired in order to implement usable, flexible C-shell / Perl / TCL programs that automate tool / flow methodologies.
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