You will be working with SoC / IP design teams to deliver next-generation Xeon Server CPU products.
You will own & drive verification of next generation server CPUs ( SOC / IPs) on emulation
You will lead validation strategy, methodology & provide technical risk assessment for validation sign-off
You will be responsible for bring-up and path clearing of features required to enable volume validation.
Drive / Participate in discussions across various disciplines to get a clear understanding of Val requirements
You will develop / drive design collaterals required for running tests which includes transactors, checkers, assembly / C++ tests, and initialization code procedures.
You will also own planning and forecasting emulator requirements.
Track progress of self / sub team to achieve goals timely and provide regular update.
Provide technical leadership & mentor / guide team members
Must have a Bachelor's degree or Master's degree in Electrical, Electronics or Computer Engineering with relevant experience of at least 8+ years
Experience with emulators such as Synopsys ZeBu, Cadence Palladium or Mentor Graphic Veloce for large scale designs
Strong understanding of Computer architecture, design principles, validation methodologies & tools
Experience with RTL design, Verilog and simulation, debug tools such as Verdi, System Verilog based verification techniques.
Experience in debugging and isolation techniques including writing checkers, monitors, assertions and necessary DPI interfaces for co-emulation environments.
Experience in SW Programming / scripting and debug such as assembly, C, C++, Perl, Python
Prior expertise in CPU, Coherency, reset, Global Flows, Power management, memory, PCIe highly desirable
Must possess strong initiative, analytical / problem solving skills, team working skills, ability to multitask and be able to work within a diverse team environment.
Inside this Business Group
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