Physical Verification Engineers
Mobiveil, Inc.
3d ago
source : Shine

Hands on experience into Physical verification at block - level , and chip - level DRC , LVS DFM , Antenna , Density Fill Routines and other Tape -

out sign - off experience is a must Experience using Synopsys ICC Tool and tape - out experience of multiple complex chips at 14 nm or below is required Experience with Mentor Calibre or Synopsys ICC and ICV is a must Proficiency with IC Validator or similar tool such as Calibre , Assura , PVS , Pegasus.

Programming experience in tcl , Perl or C , C++ Proficient in planning for and addressing electrical considerations throughout the design process (EM , IR , Noise , etc.

Physical verification flow automation exposure will be an added advantage Educational Qualification : BS / MS EE , EC , or CS,

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