Sr. Manager - SoC Verification
NXP Semiconductors
5d ago

NXP Semiconductors enables secure connections and infrastructure for a smarter world, advancing solutions that make lives easier, better and safer.

As the world leader in secure connectivity solutions for embedded applications, we are driving innovation in the secure connected vehicle, end-

to-end security & privacy and smart connected solutions markets.

Business Line Secure Transaction and Identification Group STI is searching for an passionate SOC / Verification Leader who is ready to drive SOC / IP Verification activities.

We are looking for person who has the passion to improve the way of working / solving complex problems through the verification team as well as their own direct contributions.

Experience : 12 - 18 years

The key functions and responsibilities are :

  • Definition / Architect of SOC Verification Environment
  • Define Verification methodologies to achieve first pass silicon success
  • Planning and Execution of SOC Verification with Team size of 10 Engineers
  • Manage interfaces with other teams part of Product development (i.e. system, architecture, software, design interfaces)
  • Ability to mentor other engineers and technically guide them.
  • Strong problem solving / leadership skills
  • Essential Technical Expertise :

  • Experience in Leading SoC verification activities and should have participated in successful completion of at least one SoC project across all phases from SOC Specification to Silicon.
  • Must have good understanding of ARM processor based SoC architecture and must have completed verification of two or more embedded processor based SoC.
  • Must have expertise in on ASIC verification methodologies and ASIC design flow.
  • Must have expertise on ARM based SOC software framework (multi-core multi-layer APIs)
  • Must have good experience in setting up and debugging functional and gate level simulation have multiple processors (co-simulation).
  • Must have good experience in developing BFM and functional models in Verilog / System Verilog / UVM.
  • Proven experience of the design verification methodologies such as UVM, assertion based coverage driven verification (code & functional coverage), constraint random test generation.
  • Proven experience on Formal Verification methodologies for FSM Analysis, PinMux, DMA Event and Interrupt Matrix
  • Must have complete experience on developing verification environment and test cases from planning stage to tape-out signoff.
  • Must have actively conducted functional / coverage review and bug management schemes.
  • Experience on working in SOC with complex Analog-Digital Interface will be considered as advantage.
  • Experience on working in SOC with WREAL / AMS model will be considered as advantage
  • NXPis an Equal Opportunity / Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and / or expression, marital status, status as a disabled veteran and / or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law.

    In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals.

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