We are now looking for a Senior ASIC Design Engineer - Hardware.
As a member of our ASIC backend / timing team, you'll be working on product designs, focusing on such tasks as clocks, timing convergence, chip layout planning, design optimization and automation of work flows.
Specifically you'll be focusing on full chip layout planning (partitioning, planning clock distribution and other structures, methodology), full chip timing closure signoff (using tools such as Synopsys Primetime, Cadence Tempus etc.
design optimization, and gate-level design of high-speed logic. In this role you will also interface with architecture, rtl design, layout implementation, methodology and custom design teams to drive design implementation, timing analysis / closure all the way from micro-architecture to tape-out.
What you'll be doing :
IO macros interfaces such as PCI-E, Frame-Buffer / Memory, HDMI, etc.
What we need to see :
is widely considered to be one of the technology world’s most desirable employers. We have some of the most brilliant and talented people on the planet working for us.
If you're creative and autonomous, we want to hear from you!