Senior Design Verification Engineer - System Verilog/UVM
Signon Solutions Pvt Ltd
2d ago
source :

Role :

  • Develop and execute verification plans for units and features.
  • Construct testbenches, scoreboards, and stimulus generators.
  • Implement functional coverage models.
  • Debug designs in simulation, prototyping platforms, and silicon.
  • Qualifications Required :

  • Roles requiring both 4+ and 8+ years industry experience
  • Bachelor's or Master's degree in related engineering field
  • Ability to work independently and across geographies
  • Strong domain knowledge of computer architecture
  • Skills and Qualifications Desired :

  • SystemVerilog verification development experience
  • Testbench construction using UVM or analogous methodologies
  • Scoreboards and stimulus generators for complex units
  • Industry experience with CPU microarchitecture (e.g. x86, ARM, SPARC, MIPS, RISC-V, POWER) and / or coherent caching systems
  • Software development experience in compiled (C / C++) and interpreted (Python) languages
  • Unit or feature ownership throughout the project lifecycle
  • Post-silicon validation
  • ref :

    Report this job

    Thank you for reporting this job!

    Your feedback will help us improve the quality of our services.

    My Email
    By clicking on "Continue", I give neuvoo consent to process my data and to send me email alerts, as detailed in neuvoo's Privacy Policy . I may withdraw my consent or unsubscribe at any time.
    Application form