Analog Layout Physical Design Physical Verification Engineer
Area Placement and ConsultantsArea Placement and Consultants
15d ago
source : Net4skills


Require engineers who various positions in DFT, Physical Design, Physical Verification and Analog Layout

PD (Physical Design)-

Netlist to GDSII / PD / Implementation flow / PnR / APR


Candidate has Synthesis and PD experience)

Low power design experience

ASIC / VLSI flow knowledge.

Floorplanning, Power planning,

Placement, CTS, Routing, Extraction, DFM

Congestion and timing analysis.

Sign-off flow

STA, DRC / LVS / Antenna / ERC, Power analysis, IR / EM

analysis , LEC, ECO (Timing and Functional)

Technology node

7nm , 10nm, 14nm, 20nm, 28nm, 45nm, 65nm, 90nm,130nm, 180nm (Going forward you can see tech nodes < 7nm)

PnR tools

ICC2 / ICC, Innovus (encounter), Olympus


DC (DCT / DCG) , RC / Genus

IR / EM Analysis

Redhawk, PDNA( in QC) PrimeRail


Physical / Layout Verification

Experience with

SV+UVM / OVM / VMM or Specman / eRM / UVMe

Experience with SOC with C / ASM based tests, Graphics or CPU is an added advantage

SOC System on Chip Verification; lot of IP’s (100 .)Proficient on protocols


Should have good understanding of Digital Design Flow (CDC, Low Power, HDL Simulation, Synthesis) & Tools

Preferred to have know-how of

ARM Cortex-A series Cores like A7

AMBA Busses - AXI, AHB, ATB, APB and Associated Peripheral / Debug components.

Experience of working in complex test-bench / model in Verilog, System Verilog or SystemC

System Verilog Language like C

Specman e Language

  • language like Verilog similar to SV
  • Methodology used is eRM

    Everyone is migrating to SV

    ARM based processor on above lot of IP configured, 5 10 ARM core, IP’s like PCI, USV, Ethernet, SPI, Sadus, Memory controllers, DDR, I2C

    DFT)- Design for testability : -

    Consultation for test solutions during design planning / budgeting.

    Test methodology design rules checking during RTL coding stages.

    Implementation of

    design for test (DFT) compression, automatic test generation (ATPG) for single stuck at (SSAF), Transition Delay Fault, Cell-

    aware faults, and other advanced fault models

    Experience in

    JTAG, MBIST, Scan Compression, ATPG, Fault Simulation.

    Experience with industry ATPG tools Synopsys Tetra MAX, Cadence Encounter Test or Mentor Fast Scan ATPG tools Synopsys DFT scan insertion.

    Experience with industry simulation tools such as

    VCS, Modelsim, NC Verilog etc .

    Architect and implement solutions for built-in self-test (Memory and Logic BIST) circuitry to test devices in the field.

    Participation in customer’s design and flow reviews.

    Diagnostics analysis and debug.

    Provides methodologies for test automation flow integration with design planning, RTL analysis, logic synthesis, physical design and sign-

    off verification tools (static timing, simulation, formal verification).

    Develops white-papers on methodology and other documentation as may be required for projects.

    Provides technical support / expertise for customers operating Synopsys test automation tools in a wide variety of application scenarios.

    Provide technical leadership and Mentor other people in the team.

    Experience with Design-for-Test tools, flows, and methodologies.

    PV (Physical Verification) : -


    at block-level, and chip-level

    DRC, LVS DFM, Antenna, Density Fill Routines and other Tape-out sign-off .

    Experience using Synopsys ICC Tool and tape-out experience of multiple complex chips at 14 nm or below is required

    Experience with

    Mentor Calibre or Synopsys ICC and ICV is a must

    Programming experience in tcl, Perl or C

    Proficient in planning for and addressing electrical considerations throughout the design process (EM, IR, Noise, etc.)

    flow automation

    Proficiency with IC Validator or similar tool such as Calibre, Assura, PVS or Quartz is preferable.

    Experience in foundry runset creation (for DRC / LVS / ERC / DFM), solving LVS issues,

    knowledge of foundry processes, or understanding advanced DFM requirements is highly desired

    Senior Analog Layout Engineer

    Experience : 3- 12 years

    Analog layout requirement for

    SERDES IP being done in 7nm.

    Scope involves scratch layout design.

    JD :

    This position requires 3+ Industry experience and has worked on 7nm / 10nm analog / custom layout.

    Good understanding of

    analog concepts along with experience in layout design of

    complex analog circuits is required.

    Should have worked in Layout of any one of the following is required : Power Management blocks, PLL, PHY,

    LDO, high performance ADCs, high speed IO’s or Standard cells, integration and taking the block from specification to release.

    Responsibilities will include

    floor planning, DRC / LVS verification and fix,

    Reliability Analysis and fix, implementation.

    Should have good debugging skills.

    Tiempo completo

    Habilidades profesionales Ver más

    Conocimientos Ver más

    Experiencia laboral (en años)

    3 - 12

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