Mgr I, ASIC Physical Design
Bangalore, INDIA
7h ago

and Requirements

Physical Design and STA Engineer

GPIO+ team is ramping up Test Vehicle Activity to enhance Si learning and provide robust solution to our customers. We are looking for Phyiscal Design and STA engineer with below requirements

Major Responsibilities :

  • Execute RTL to GDS flow through different stages of Handoff, Synthesis, Floor-planning, Power-planning, Synthesis, Equivalence checking, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM / IR / ESD signoff
  • To meet design PPA targets and reporting KPI figures
  • To understand and moderate design constraints working with RTL design team
  • Additional Responsibilities :

  • Setup and maintain RTL2GDS design flow and methodology including required automations to enable robust and efficient execution
  • Train and help ramp up junior team members
  • Ensure timely design reviews at appropriate stages of development cycle
  • Act as the Interface with other design domains
  • Regularly evaluate and deploy new tools and methodologies to ensure robust and efficient execution
  • Key Qualifications and skills :

  • BS / BTech / MTech with 8 yrs+ relevant PD and STA experience
  • Rich experience in Finfet and FDSOI technologies of digital design, implementation and signoff of partitions and full chip
  • Fully hands-on with Synopsys tool suite (DC, VC -Spyglass / LP / Formal, FC / ICC2, StarRC-XT, Primetime, ICV)
  • Strong scripting skills in any one of the followings : C / C++, tcl, perl or python
  • Desirable qualifications :

  • Experience in ESD structure integration for silicon qualification
  • Basic exposure of On-chip characterisation methodology and application in a design
  • Experience of implementing full IORing with co-design
  • Experience in implementing partitions to fulfil Mixed signal IP silicon qualification of DC / AC characteristics including HTOL and ESD qualification
  • Prior experience and understanding of on-chip characterisation circuits design and integration
  • Our Silicon IP business is all about integrating more capabilities into an SoC faster. We offer the world’s broadest portfolio of silicon IP predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors.

    All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications.

    And get differentiated products to market quickly with reduced risk.

    At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence.

    The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security.

    If you share our passion for innovation, we want to meet you.

    Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

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