Job Description and Requirements
Synopsys Designware DDR IP is uniquely positioned in the industry as one of the most complex and high performing IP, in terms of interface, feature support as well as deployment acrss a wide spectrum of customer products.
We have multiple full time positions with experience level 0-8 years available for supporting IP level as well as sub-system level DFT and ATPG work for our next generation of development.
Prior experience on SOC or IP level DFT / ATPG work is strongly required for senior candidates
Strong knowledge of DFT features - Scan, ATPG, stuck-at ,at-speed, memory BIST, JTAG standards & Boundary scan
Scan insertion and ATPG experience for stuck-at , transition, bridging and IDDQ methodologies
Coverage improvement and DRC analysis using Tetramax ,DFT compiler & spyglass DFT
ATPG pattern generation for various fault models and gate level simulation (timing & no-timing ) and debug
Experience in RTL analysis, logic synthesis, physical design and sign-off verification tools (static timing, formal verification) is a plus
Understand and support the design architectures and clocking structures to create the Scan / MBIST / DFT timing and physical design constraints
Experience with DFT / physical design methodologies and TCL / perl / Shell scripting is required
Experience in post silicon debug for DFT bring up is a plus
Strong communication skills and a desire to work with a highly skilled team of global multi-site teams is highly desirable.