Position Title : IP Circuit Design and Layout Development Engineer Work Area : Foundry IP Development Location : Bangalore Summary of Role :
Work with a IP Development team on the circuit design and layout of IP designs, such as Standard Cell Logic libraries, and IO libraries in various technology nodes.
Essential Responsibilities :
Use industry standard design tools to perform gate / transistor level electrical circuit design and physical layout, circuit design verification / simulation, and electrical and physical rules generation for Foundry circuits.
Some emphasis on Front End Design Tools with solid knowledge of Verilog design language.
Required Qualifications :
Education : BS + 5 years’ experience, or MS + 3 years’ experience in Electrical or Computer Engineering
Minimum of 3 - 5 years of experience with digital / analog IP circuit design, layout, and timing experience
Language Fluency Fluent in English Language written & verbal.
Must have transistor level electrical circuit design understanding.
Must be able to interpret electrical design specifications
Applicant should have a proficient knowledge of and experience with EDA tools for schematic and physical layout, design rule checking (DRC), layout versus schematic checking (LVS, schematic and layout extraction, methodology checking, circuit simulation and analysis, and various physical and electrical rules
Knowledge of AIX / NFS, Linux, Shell, Tcl, Perl
Must have good technical verbal and written communication skills and ability to work with cross functional teams is necessary
Candidates who are self-driven and have worked in a global team environment with a successful track record of on-time high quality IP design creation.
Be able to collaborate with program and technical design leads on multiple concurrent projects.
Should have excellent problem solving skills, written & oral communication, teaming & inter-personal skills
Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs
Additional Eligibility Qualifications : Preferred Qualifications :
Should have experience with various types of layout methods for transistor level circuit design
Knowledge of the end-to-end IP and Chip design cycles
Knowledge in RF technologies (Bulk, CMOS & SOI) process is desired.
Project management, Schedule development, SOW creation skills are desired.