At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
The candidate will be expected to work with a team of engineers
Write synthesizable designs (RTL) in Verilog / VHDL to test various domains and features of RTL Compiler. Run Physical Synthesis and correlate the physical synthesis results with backend tools.
Debugging the correlation and QoR gaps. Write programs and scripts to help automate tests. Contribute to make the solution better by working with RnD teams.
We’re doing work that matters. Help us solve what others can’t.