What will you be doing in this role? (Responsibilities)
Micro-architecture development and implementation of IPs working closely with Systems / Architecture teams.
Quality checks of the implemented RTL for LINT, CDC and DFT rules and clear documentation of exceptions and waivers.
Synthesis and timing closure of implemented IP along with equivalence checks.
Provide quality documentation of IP implementation and other deliverables post systematic reviews.
Work closely with IP and SoC verification teams to achieve high quality IP delivery.
Provide support to SoC Integration, constraint development and timing closure.
Contribute and drive quality / cycle time improvement methodologies as a part of the development process.
Be a team player working across functional teams responsible for development of IP / SoCs from spec to silicon.
What do we expect from you? (Mini Qualifications)
Strong RTL design experience of 1-3 years with IP designs for microcontrollers expected.
Design experience with high performance Bus Architectures, Memory Controllers for volatile / non-volatile memories and Analog-Mixed signal IPs is required.
Experience with Hardware Accelerators for mathematical functions and control peripheral designs will be a plus.
Must have strong multi-clock domain design knowledge and expertise in Clock Domain Crossing (CDC) analysis tools.
Experience in timing constraint development at SoC level and timing analysis is preferred.
RTL Synthesis and LEC experiences are a must have.
Experience with scripting and automation including IPXACT exposure would be an added bonus.
Preferred Skills / Experience
4-7 years of experience in IP Development, SoC integration and implementation.
Strong experience with Linting, CDC, Synthesis, Equivalence check and timing checker tools are required.