Physical Design CAD Data Management Lead
Bengaluru, Karnataka, India
3d ago

Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves.

Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure.

You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing.

Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

With your technical expertise, you lead projects in multiple areas of expertise (i.e., engineering domains or systems) within a data center facility, including construction and equipment installation / troubleshooting / debugging with vendors.

You will be part of Google’s Devices and Services PA Silicon Engineering Productivity (EngProd) team and contribute to the development of differentiated products that combine the best of Google AI, hardware, and software.

The charter of Silicon EngProd is to develop and maintain the underlying foundational infrastructure, and continually improve the productivity our Silicon team who develop custom silicon (chip) solutions

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences.

We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.


  • Be responsible for developing a state of the art PD CAD flows for silicon from ground up.
  • Develop and support a hierarchical data management system for data hand off.
  • Build an audit framework to enable design audits and checks. - Work with designers to develop a tapeout signoff checklist and enable dashboards
  • Work across implementation and signoff domains to enable seamless interactions. Work with foundries to figure out foundry deliverables and build release packages.
  • Work directly with design teams and building data management infrastructure that can scale across multiple projects and cutting edge technology nodes.
  • Drive data handshake between different domains and build systems which qualify the designs for tapeout.

    Minimum qualifications :

  • Bachelor's degree in Electrical or Electronics Engineering with 5 years of experience in ASIC design implementation and convergence, or equivalent practical experience.
  • Experience with block implementation and signoff flowsScripting experience writing production scripts for PNR tools.
  • Experience working with external vendors and driving design improvements.
  • Preferred qualifications :

  • CAD flow development experience.
  • Familiar with full chip timing and signoff convergence methodology.
  • Knowledge of cutting edge technology node across foundries hierarchical full chip implementation and signoff experience.
  • Evaluate multiple vendor solutions and drive tool decisions.
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