Principal Engineer Elect Design
Bangalore, India
4d ago

RTL Design Engineers

  • Candidate will be responsible for building / maintaining highly configurable and reusable IO Subsystems (Note : An IO Subsystem is a logic IP that processes the IO Pads / IO Ring information and builds required logic to allow multiple on-chip peripherals to share the same IOs in a configurable manner)
  • Candidate will be responsible for RTL design for integration of IO pads into SoC, building the required multiplexing logic and necessary power control signals integration.
  • Must have worked in ASIC Design flow for more than 8 yearsMust be strong in scripting using PERL.Must be familiar with RTL design for ASIC development using Verilog.
  • Must be familiar with LINT (LEDA / Spyglass), Clock-Domain-Crossing analysis, UPF, MVRC, Synthesis, Timing constraints and debugging STA reports.

    Strong mindset towards automation of repetitive work.Strong fundamentals in DFT / Fault-grading and / or hands on experience.

    Proven track record of working with Chip Leads and Cross Functional Teams for IP delivery into ASIC / SoC design.Strong written and verbal communication skills

    What we offer you at Bangalore - Flexible working conditions- Part-time work possible (also during parental leave)

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