Formal verification Engineer
Qualcomm Technologies, Inc.
India - Bangalore
1d ago

Overview Qualcomm is a company of inventors that unlocked 5G - ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives.

But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-

changing technologies and products. This is the Invention Age - and this is where you come in. Job OverviewVerification Design Automation Engineers are responsible for developing, implementing, and deploying automated methodologies and tool flows that are used to validate a multitude of wireless chips and IP cores / blocks.

As part of the Qualcomm Mobile and Computing (QMC) engineering team, this position plays a critical role in driving next-

generation verification methodologies through the deployment of semi- and full-custom EDA tools that are used widely across the globe by the various ASIC digital design teams.

As a key member of the EDA Verification Design Automation team, you will develop and contribute directly to the technical aspects of many advanced Verification methodologies and initiatives.

Key areas of focus include working in the Formal Verification domain in the following areas : Working closely with cross-

functional teams across all chips and IP Cores / Blocks to develop / deploy efficient methodologies in Formal Verification spanning across various Apps / features for VC Formal / Jaspergold tools, aiding users in troubleshooting of issues, evaluation of third-

party Formal Verification tools to gauge deficiencies and suggest improvements. Minimum Qualifications : -Bachelor's degree in Engineering, Information Systems, Computer Science, or related field-

4 - 10 years of work experience in Formal Verification methodology development / deployment / debug-Working knowledge of SystemVerilog Assertions -

Scripting knowledge / skills in Tcl-Tk, Perl Minimum Qualifications Bachelors degree

5 Plus years experience

Preferred Qualifications Job OverviewVerification Design Automation Engineers are responsible for developing, implementing, and deploying automated methodologies and tool flows that are used to validate a multitude of wireless chips and IP cores / blocks.

As part of the Qualcomm Mobile and Computing (QMC) engineering team, this position plays a critical role in driving next-

generation verification methodologies through the deployment of semi- and full-custom EDA tools that are used widely across the globe by the various ASIC digital design teams.

As a key member of the EDA Verification Design Automation team, you will develop and contribute directly to the technical aspects of many advanced Verification methodologies and initiatives.

Key areas of focus include working in the Formal Verification domain in the following areas : Working closely with cross-

functional teams across all chips and IP Cores / Blocks to develop / deploy efficient methodologies in Formal Verification spanning across various Apps / features for VC Formal / Jaspergold tools, aiding users in troubleshooting of issues, evaluation of third-

party Formal Verification tools to gauge deficiencies and suggest improvements. Minimum Qualifications : -Bachelor's degree in Engineering, Information Systems, Computer Science, or related field-

4 - 10 years of work experience in Formal Verification methodology development / deployment / debug-Working knowledge of SystemVerilog Assertions -

Scripting knowledge / skills in Tcl-Tk, Perl Education Requirements Required : Bachelors of Science degree in Computer Engineering, Computer Science, or Electrical Engineering.

Preferred : Masters of Science degree in Computer Engineering, Computer Science, or Electrical Engineering, and / or prior industry experience.

Keywords Low Power verification, Verification, Emulation, EDA, UPF1.0, UPF2.0 OVM, UVM, Electronic Design Verification, VHDL, Verilog, Perl, Python, Tcl, C / C++

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