SOC Design Engineer
Intel
Bangalore, KA, IN
1d ago

Job Description

The Standard Cell Team is part of the Design Enablement / Advanced Design Group in Technology Development. Its main charter is in design, development, QA, and delivery of Testchip / benchmarking standard cell libraries to enable best-in-class IP and product design on all generations of Intel technology.

The candidate is responsible for characterization of standard cell library and view generation, own delivery of standard cell library to the design package, generate all required views (NDM, FRAM, ATPG,UDFM etc), strive to ensure the quality of releases, drive implementing QA checks to improve robustness of the delivery (consistency and completeness of the views, usability in the EDA tools), work with vendors to get the PVT char setup and drive generation of custom PVTs are required by methodology / design team (Silicon Smart), establish best in class QA methodology for maximum coverage, understand, analyze and drive improvements to existing methodologies, automation of repeatable tasks for productivity improvements, documentation of work flows, issues, debugs, lessons learned from the projects and presentations to the team, mentor and enhance the skill set of junior team members.

Qualifications

One must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications :

  • One must possess Master degree(ME / MTech) with VLSI specialization. A minimum of 5+ years of relevant experience in standard cell layout design, silicon implementation, and / or process technology.
  • Desired Skills and Experience :

  • Understanding of characterization methodologies for timing, power, constraints, related trends like LVF, OCV etc. familiarity with simulators, liberty syntax requirements, CCS, statistical characterization, Verilog models, UDFM, STA & power analysis tools and familiarity with characterization challenges of special cells like synchronizers, multibit cells, etc.
  • Ability to drive a library development end to end, including interface with stakeholders.

  • Understanding of PDK / characterized models and ensure they help meet the PPA targets of the library. Ability to derive useful information from liberty files to deduce cell / library performance, trend analysis etc.
  • Work with benchmarking team / setups to understand impact of library at block level, interpret results and drive feedback to improve quality of layouts, designs.

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