Director SoC Integration
4d ago

NXP Semiconductors N.V. (NASDAQ : NXPI) enables secure connections and infrastructure for a smarter world, advancing solutions that make lives easier, better, and safer.

As the world leader in secure connectivity solutions for embedded applications, NXP is driving innovation in the automotive, industrial & IoT, mobile, and communication infrastructure markets.

Built on more than 60 years of combined experience and expertise, the company has over 29,000 employees in more than 30 countries and posted revenue of $8.88 billion in 2019.

Responsibilities would include :

  • Fully own the Design, DFT, Verification for Subsystems / SOCs from Initial specification till Tapeout and beyond
  • Supervising RTL / DFT / Verification Sign off, timing constraints, CDC and work with different functions like verification, synthesis, etc.
  • to get to a production quality Silicon

  • Leading various aspects of Test architecture including Scan & ATPG, Memory BIST, Logic BIST, Analog / PHY test and post-silicon support with test pattern generation
  • Manage, build and develop teams of fresh and experienced engineers. Train and mentor fresh engineers for increased productivity
  • Build up strong collaboration with other R&D teams like Architecture, SOC Implementation, DIG IP, Mixed-Signal IP, Design Enablement, Packaging, Board design and Validation to achieve all project milestones
  • Influences technical strategy to drive innovation, e.g., products, technology and / or patents) that consistently contributes to significant revenue and profit
  • Directs and controls the activities of a broad functional area through several department managers within the company.
  • Responsible for people development, goal setting and team performance.
  • Developing project plans including resource, schedules, progress reports, verification plans, signoff checklists and tracking milestones
  • Holding periodic internal and external reviews to ensure quality and meet delivery criteria
  • Working with various EDA vendors to deploy next gen Design technologies
  • Ensure quality adherence during all stages of the project life cycle. Also carry out a thorough analysis of existing processes and recommend and implement the process improvements to ensure Zero Defect’ chips
  • Ensure that SMART metrics are established to measure the Design Verification processes and goals.
  • Job Qualifications

    BTech / MTech / PhD with 15+ years’ experience in Semiconductor industry. Candidate should be an experienced manager having experience of leading a team in SoC integration / Verification.

    Experience with various emulation / accelerator methods and use-case environments is an additional benefit.

  • Experience of SoCs based on ARM A / R / M Multi Core Architecture, RISC V, Power PC, etc.
  • Experiences in all aspects of DFT, including scan & ATPG, memory BIST, logic BIST, analog test, and post-silicon support.
  • High Speed Peripherals like DDR, PCIe, ENET, GPU, VPU (Video Processing Unit)
  • NIC / FlexNOC interconnect, Flash memory subsystem architecture knowledge
  • Strong domain knowledge of Clocking, System modes, Power management, debug, interconnect, Functional Safety(ISO26262), security and other architectures
  • Experience of working on Gate Level Sims with strong concepts of CDC, RDC, Power Aware GLS.
  • Low Power intent verification using CPF, UPF
  • FPGA / Emulation / Prototyping using HAPS / Palladium / Zebu would be an additional advantage
  • Power management understanding
  • Job Location

  • Bangalore, India
  • Report this job

    Thank you for reporting this job!

    Your feedback will help us improve the quality of our services.

    My Email
    By clicking on "Continue", I give neuvoo consent to process my data and to send me email alerts, as detailed in neuvoo's Privacy Policy . I may withdraw my consent or unsubscribe at any time.
    Application form