Infra IP Design - Trace & Debug IP Sr.Staff Engineer
3d ago

Company :

Qualcomm India Private Limited

Job Area :

Engineering Group, Engineering Group >

Job Overview :

Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives.

But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products.

This is the Invention Age - and this is where you come in.

Job Description

Micro-Arch, RTL Design ownership of Trace & Debug IP for the next generation System-on-chip (SoC) for smartphones, tablets and other product categories.

Trace and Debug IP's are based on ARM Core sight architecture, critical for System performance profiling and failure debug.

Job responsibilities include

  • Develop micro arch design specification for Trace & Debug features optimized for performance, area, power, Software use cases
  • Implement design spec in RTL coding language, qualify code through all required quality checks like Lint, CDC, Synthesis / DFT / low power checks
  • Work closely with Design verification, emulation teams on failure debugs, code / functional coverage closure
  • Interact with SoC design and physical design implementation teams on timing closure and area / power optimization
  • Debug and root cause post silicon issues in collaboration with SW and test teams
  • Work with SoC level performance modeling team on latency, bandwidth analysis
  • Required skillset include

  • VLSI logic design expertise
  • Hands-on experience with Verilog RTL coding, DRC checks, low power design
  • Knowledgeable about on-chip interconnect protocols like APB / AHB / AXI / ACE / ACE-Lite
  • Good understanding of the ASIC design convergence cycle in terms of architecture, micro-architecture, synthesis, timing closure and verification
  • Strong debugging, Analytical and problem-solving skills
  • Communication and collaboration skills to work with a large world-wide design organization
  • Desired skillset include

  • Understanding of ARM Core sight architecture
  • Experience in designs optimized for low power - Dynamic clock gating, Logic / Memory power collapse
  • Proficiency in Scripting languages (Python or Perl) for Automation initiatives, C / C++ / SystemC for performance models
  • Working knowledge of Synthesis, DFT, LEC, functional cover points / assertions, code coverage analysis, formal verification
  • Educational Requirements

    Bachelor / Master’s Degree in Electronics & Communication / Micro Electronics

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