Principal Verification Engineer
Summit Partners, L.P
Pune, IN
8d ago

req373 India - APM Pune

Headquartered in Lowell, Massachusetts, MACOM is certified to the ISO9001 international quality standard and ISO14001 environmental management standard.

MACOM has multiple design centers, Si, GaAs and InP fabrication, manufacturing, assembly and test, and operational facilities throughout North America, Europe, Asia and Australia.

In addition, MACOM offers foundry services that represents a key core competency within our business. The foundry provides access to, and control of our broad range of proprietary technologies in an asset light, cost effective structure.

MACOM sells and distributes products globally via a sales channel comprised of a direct field sales force, authorized sales representatives and leading industry distributors.

Our sales team is trained across all of our products to give our customers insights into our entire portfolio.

Our global organization of skilled engineers is driven every day to solve the world’s most demanding wireless and wireline application challenges.

We’re proud of our more than sixty years’ of hands-on experience designing and building analog semiconductor technology across the RF to Light spectrum.

This role is being sourced, to be fill over the next 3 to 6 months.

Principal Verification Engineer

Job Description :

  • Independently architect UVM based verification environments including drivers, monitors, scoreboards, functional checkers, functional coverage
  • Innovative in functional coverage techniques and stress verification with testing all corners of DV Passing / Failing / Error / breaking scenarios for DUT
  • Own verification at module and / or full chip level
  • Proficiency in System Verilog and advanced UVM methodologies is a must
  • Good experience in System Verilog assertions
  • Own the development of test plans, test environments and test suites used to verify complex Ethernet and Microcontroller SOC products
  • Prior experience as a verification lead is preferred
  • Prior experience of working with and guiding the junior members of the team is required
  • Responsibilities :

  • Product verification test plan specification
  • Drive verification methodologies and practices
  • Develop System Verilog verification IP
  • Develop chip / block level test environments
  • Develop and debug test suites
  • Lead and mentor other verification engineers
  • Requirements :

  • Strong understanding of ASIC methodologies and tooling
  • Strong understanding of UVM, SysteVerilog and OOP programming
  • Ethernet , Microcontroller based SOC verification experience
  • Experience Level : 10+ years of ASIC verification experience.
  • Prior experience as a verification lead is a plus.
  • Apply
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