This position is for an experienced layout engineer in the areas of custom circuits, memories - SSA / RF (SRAM / Register File) / ROM design in gFIT Circuits COE Team.
In this position you will be working in a team responsible for delivering high quality for graphics projects. You would also be working on implementing layout for several memory and custom designs for graphics The responsibilities involve working at transistor level layout and includes ownership of implementation of the design as well as converging them for LVS / DRC / Noise and RV(EMIR).
It will also involve evaluating and designing custom hard IP's with focus on power, performance and area. The role would require strong communication, problem solving, time management and multitasking skills.
Candidate must possess a Master's degree in Electrical / Electronics / Computer Engineering and 3+ years of experience OR Bachelor's degree and 6+ years of experience.
Relevant experience should be in CMOS Layout Design, with exposure to Industry standard tools for drawing layouts (Virtuoso / custom explorer) DRC&LVS (Calibre / ICV), Extraction (StarRC / CCI), EMIR low (Totem / XA).
Knowledge of Genesys for layout drawing is desirable. Knowledge of design as well as scripting knowledge in Skill / Perl / Tcl, experience with UNIX, and expertise in layout automation will be an added advantage