Verification Engineer - System Verilog (5-8 yrs) Bangalore (Semiconductor/VLSI/EDA)
2d ago
source :

We are looking for candidates with hands on experience in system verilog, UVM .

  • Solid UVM and SV skill set. Good debugging skills using DVE or Debussy.
  • Good experience in SV assertion development and verification. Good experience in formal property verification. Also good Experience in DFT functional verification using JTAG, IJTAG etc.
  • Experience in PCIE, DDR, HBM, Clocking etc. verification is a plus.
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